View CXA1315_24018.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CXA1315M/P
8-bit D/A Converter Supporting with I2C Bus
Description The CXA1315M/P is developed as a 5-channel 8bit D/A converter supporting with I2C bus. Features * Serial control through I2C bus * 5-channel 8-bit D/A converter * Built-in 4general-purpose I/O ports (Digital I/O) * I/O can be specified to respective ports independently * Selection of 8 slave addresses possible through address select pins (3 pins) Applications The IC, which cannot support I2C bus, can support it by connecting its control pin to the CXA1315M/P. Structure Bipolar silicon monolithic lC Absolute Maximum Ratings (Ta = 25C) * Supply voltage VCC 12 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD 960 mW Operating Conditions * Supply voltage * Operating temperature CXA1315M 16 pin SOP (Plastic) CXA1315P 16 pin DIP (Plastic)
VCC Topr
8.2 to 9.8 -20 to +75
V C
Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defind by Philips. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E88Z45D78-PS
CXA1315M/P
Pin Configuration (Top View)
I2C bus Slave address select pin SW I/O
SAD2
SAD1
SAD0
SCL
16
15
14
13
SW3
VCC
12
11
10
1
2
3
4
5
6
7
DAC2
SW1
DAC1
SW0
DAC4
DAC0
SW I/O
DAC3
DAC output
Block Diagram
SAD2 SAD1 SAD0 Level Conversion SW0 to 3 Open collector LATCH Level Conversion
I2C BUS SDA SCL Level Conversion I2C Decoder
Power On Reset LATCH LATCH LATCH LATCH LATCH
VCC
DAC VCC
DAC
DAC
DAC
GND
SW2
9 8
SDA
DAC
REG
AMP
AMP
AMP
AMP
AMP
DAC4 GND
DAC3
DAC2
DAC1
DAC0
-2-
CXA1315M/P
Pin Description No. 1 2 9 10 Symbol SW1 SW0 SW2 SW3 Equivalent circuit
VCC VCC
Description I/O pin for genera-purpose I/O port VILmax: 1.5V VIHmin: 3V VOLmax: 0.4V
150
4.5k
14
SDA
VCC VCC
SDA I/O pin for I2C bus
3 4 5 6 7
DAC4 DAC3 DAC2 DAC1 DAC0
56 20k 20k
22k
D/A converter output pin
8
GND
VCC VCC
GND pin
11 12 13
SAD0 SAD1 SAD2
150
Slave address input pin Input at positive logic VILmax: 1.5V VIHmin: 3V
4.5k
15 16
SCL VCC
SCL input pin for I2C bus Power supply pin (Ta = 25C, VCC = 9V) Symbol lcc Test circuit 1 Test conditions DAC 0 to 4 = 127 Min. Typ. Max. Unit 8 11 15 mA
Electrical Characteristics No. 1 Item Circuit current
D/A Converter Block 2 Differential linearity Minimum output voltage Maximum output voltage Output current Output impedance Repple rejection DLE 1
V (DAC0 to 4 = n + 1) - V (DAC0 to 4 = N) x 128 - 1 V (DAC0 to 4 = 191) - V (DAC0 to 4 = 63) n = 0 to 127
-1
0
+1.1 LSB
3 4 5 6 7
Vmin Vmax Iout Zo Grip
1 1 2 2 3
DAC 0 to 4 = 0 DAC 0 to 4 = 255 Current that can be flowed from Pins 3 to 7 DAC 0 to 4 = 127, V (-1mA) - V (1mA) 2mA
0.1 8.3 -1 0 --
0.4 0.62 8.5 8.9 +1 3 6
V V mA dB
DAC 0 to 4 = 127, REF = 0 Superimose 100Hz to VCC, 1Vp-p -3-
-60 -40
CXA1315M/P
SW, SAD Pins No. 8 8 9 10 11 Item Low level input voItage High level input voltage Low level input current High level input current Low level input voltage Symbol Test circuit VIL VIH IIL IIH VOL 4 4 4 4 5 Test conditions Input voltage where ST0 to ST3 become "0" Min. Typ. Max. Unit -- -- -- 0 0 0.2 1.5 -- +10 +10 0.4 V V A A V
Input voltage where ST0 to ST3 become "1" 3.0 lnput current when 0.4V is applied lnput current when 4.5V is applied SW 0 to 3 = 1, Output voltage when 1mA flows in -10 -10 0
I2C Bus Block Items (SDA, SCL) No. 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Item High level input voltage Low level input voltage High level input current Low level input current Low level output voltage, at 3mA flow to SDA (Pin 14) Maximum flowing current lnput capacitance Maximum clock frequency Data change minimum waiting time Data transfer start minimum waiting time Low level clock pulse width High level clock pulse width Minimum start preparation waiting time Minimum data hold time Minimum data preparation time Rise time Fall time Minimum stop preparation waiting time Symbol VIH VIL IIH IIL VOL IOL CI fSCL tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO Min. Typ. Max. 3.0 -- 5.0 -- 1.5 0 -- 10 -- -- 10 -- -- 0.4 0 ---- 3 -- 10 -- -- 100 0 4.7 -- -- 4.0 -- -- 4.7 -- -- 4.0 -- -- 4.7 -- -- ---- 5 250 -- -- -- 1 -- -- 300 -- 4.7 -- -- Unit V V A A V mA pF kHz s s s s s s ns s ns s
I2C bus load conditions: Pull-up resistance 4k (Connected to +5V) Load capacitance 200pF (Connected to GND)
I2C Bus Control Signal
SDA tBUF tR tF tHD; STA
SCL tLOW P S tHD; STA tHD; DAT tHIGH tSU; DAT Sr tSU; STA tSU; STO P
-4-
CXA1315M/P
Electrical Characteristics Measurement Circuit Measurement Circuit 1
+9V 10 16 15 14 13 12 11 10 9 0.022 I2C BUS 5V
Measurement Circuit 2
+9V 10 16 15 14 13 12 11 10 9 0.022 I2C BUS
CXA1315M/P 1 2 3 4 5 6 7 8 1 2 3
CXA1315M/P 4 5 6 7 8
100p 100p 100p 100p 100p
100p 100p 100p 100p 100p
1mA
Measurement Circuit 3
100Hz, 1Vp-p 0.022 +9V 10 16 15 14 13 12 11 10 9 I2C BUS
Measurement Circuit 4
+9V 10 16 15 14 13 12 11 10 9 0.022 I2C BUS V4
CXA1315M/P 1 2 3 4 5 6 7 8 1 2 3
CXA1315M/P 4 5 6 7 8
100p 100p 100p 100p 100p
V4 =
1.5V (No.8) 2.0V (No.9) 0.4V (No.10) 4.5V (No.11)
Measurement Circuit 5
1mA
+9V 10
0.022
I2C BUS
16
15
14
13
12
11
10
9
CXA1315M/P 1 2 3 4 5 6 7 8
-5-
CXA1315M/P
Definition of I2C Bus Register
MSB 0 1 0 0 SAD2 SAD1 SAD0 LSB R/W
R/W 0: SLAVE RECEIVER 1: SLAVE TRANSMITTER SAD0 to 2:11 to13 pin 0: "Low" 1: "High"
* * * * * With the lC reset all registers are reset to "0" : Not defined x: Don't care Sub address is auto incremented lt can be used as a 6-bit D/A converter by setting the lower two bits of DAC0 to 4 registers to "0", but take care that the max. voltage of DA output will lower about 100mV compared with the use of 8 bits.
Control Register Sub address xxxxx000 xxxxx001 xxxxx010 xxxxx011 xxxxx100 xxxxx101 Bit 7 REF Bit 6 Bit 5 Bit 4 Bit 3 SW3 DAC0 (8) DAC1 (8) DAC2 (8) DAC3 (8) DAC4 (8) Bit 2 SW2 Bit 1 SW1 Bit 0 SW0
Status Register
Bit 7 PONRES
Bit 6 0
Bit 5 0
Bit 4 0
Bit 3 ST3
Bit 2 ST2
Bit 1 ST1
Bit 0 ST0
-6-
CXA1315M/P
In brackets ( ) number of bits REF (1) : Switches D/A converter reference voltage 0: Standardizes the inner regulator 1: Standardizes voltage resistance divided from Vcc (1) : Selects ON/OFF of Pins 1, 2, 9 and 10 (Each pin is the open collector output of NPN transistor) 0: OFF 1: ON (8) : Digital data input register of D/A converter 0: Output voltage turns to minimum 255: Output voItage turns to maximum (1) : Detects POWER ON RESET 0: Master passes from the bus and is reset to "0" after having read this status 1: Sets to "1" when power supply is turned on or when there has been a power dip (1) : Detects and registers the voltage condition of Pins 1, 2, 9 and 10 0: 1.5V and below 1: 3.0V and above Note) SW0 to 3 effective during "0"
SW0 to 3
DAC0 to 4
PONRES
ST0 to 3
I2C Bus Signal There are 2 signals in I2C bus. SDA (Serial Data) and SCL (Serial Clock). SDA is double-way. * As SDA is bidirectional it has 3 state outputs, H, L and Hi-Z.
H
L
Hi-Z
L
* I2C transfer begins with Start Condition and ends with Stop Condition.
Start Condition S Stop Condition P
SDA
SCL
-7-
CXA1315M/P
* I2C data write (Write from I2C controller to IC)
At "L" during write MSB SDA Hi-Z MSB LSB Hi-Z
SCL S MSB
1
2
3
4
5
6
7
8
9
1
8
9
Address LSB Hi-Z Hi-Z
ACK
Sub Address
ACK
1
8
9
1
8
9
DATA (n) Hi-Z
ACK
DATA (n + 1) Hi-Z
ACK
DATA (n + 2)
The number of data that can be 8 9 1 8 9 P transferred at a time is confined to units of 8-bit that can be set as required. Sub Address is incremented automatically.
DATA
ACK
DATA
ACK
* I2C data read (Read from IC to I2C controller)
At "H" during read
SDA
Hi-Z
SCL S
1
6 Address
7
8
9 ACK
1
7 DATA
8
9 ACK P
* Read timing
MSB IC output SDA LSB
SCL
9
1
2
3
4
5
6
7
8
9
Read timing
ACK
DATA
ACK
Data read is performed with SCL rise.
-8-
CXA1315M/P
Application Circuit
I2C BUS 10k +9V 10 16 15 14 13 12 11 10 9 0.022 10k General-purpose output port
CXA1315M/P 1 10k 10k 10k 2SC2785 D/A converter output 2 3 4 5 6 7 8
10k General-purpose input port 10k 2SC2785 Slave address for 4Ch and 4Dh 10k
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Characteristics Diagram
D/A converter output temperture characteristics (REF: 0)
0.1 VCC = 9V 0.1
D/A converter output temperture characteristics (REF: 1)
VCC = 9V
Voltage variation at. 25C [V]
Data: 0 Data: 0 Data: 128 0 Data: 128 Data: 255
Voltage variation at. 25C [V]
Data: 0 Data: 128 0 Data: 255 Data: 0 Data: 128
Data: 255
Data: 255 -0.1 -25 0 25 T [C] 50 75 -0.1 -25 0 25 T [C] 50 75
-9-
CXA1315M/P
Package Outline CXA1315M
Unit: mm
16PIN SOP (PLASTIC)
+ 0.4 9.9 - 0.1
+ 0.4 1.85 - 0.15
16
9 0.15 + 0.2 0.1 - 0.05
+ 0.3 5.3 - 0.1
7.9 0.4
0.45 0.1
1.27
+ 0.1 0.2 - 0.05
0.24 M
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE PACKAGE MASS SOP-16P-L01 SOP016-P-0300 LEAD MATERIAL COPPER ALLOY 0.2g LEAD TREATMENT EPOXY RESIN SOLDER PLATING
- 10 -
0.5 0.2
1
8
6.9
CXA1315M/P
CXA1315P
16PIN DIP (PLASTIC)
+ 0.1 0.05 0.25 -
0 to 15
EPOXY RESIN SOLDER PLATING COPPER ALLOY 1.0 g
16
9
1 2.54
8
+ 0.4 3.7 - 0.1
0.5 MIN
0.5 0.1 1.2 0.15
3.0 MIN
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE DIP-16P-01 DIP016-P-0300 Similar to MO-001-AE LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
16PIN DIP (PLASTIC) 300mil
7.62
Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type.
+ 0.3 6.4 - 0.1
+ 0.4 19.2 - 0.1
19.35 0.5
16
9
6.35 0.127
+ 0.1 0.28 - 0.06
0 to 10
1
8 2.54 0.254
0.508 MIN
1.016
0.457 0.076
3.1 MIN
5.08 MAX
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE DIP-16P-191 DIP016-P-0300-AU MS-001-AA LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER 1.0g
- 11 -
7.62

▲Up To Search▲

Price & Availability of CXA1315

	To Download CXA1315 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .